VLSI SALARY
ROLE FAMILY

Static Timing Analysis

Timing constraints, analysis and closure work.

OFFICIAL EMPLOYER DISCLOSURES

Current source-linked ranges

1 official posting mapped to this role family. These are listing-specific base-pay ranges, not a market median.

1 official ranges

Synopsys2026-08-26

R&D Engineering, Principal Engineer — Static Timing Analysis

Sunnyvale, California, United States

$191,000$286,000
Pay type
Base salary
Period
Not stated
Currency
USD

Employer-disclosed U.S.-wide base-salary range for an EDA/STA principal-engineer role.

OPEN OFFICIAL POSTING

Each card reproduces only the employer-disclosed base range and its stated scope. It is not converted into a market estimate, annualized unless the posting says so, or combined with bonus/equity.

Community compensation cells

No anonymous submission cell currently meets the publication threshold. Official occupational wage context remains available in the public data explorer, but it is not treated as a role-specific VLSI Salary estimate.